MORE INFORMATION ABOUT WAFER &
DEVICE PACKAGING AND INTERCONNECT

In a very short time spell, WDPI has become the leading force in back-end semiconductor industry editorial coverage; it covers the entire spectrum of new processes including wafer fab BEOL, and the familiar, yet constantly-evolving, back-end. The magazine encompasses all facets of packaging and high density interconnects with global distribution via both a print and a digital edition.

WDPI magazine, launched at SEMICON West 2009, was founded by some long-time semiconductor and electronics manufacturing industry manufacturing and publishing veterans. We have the largest verified print circulation of any magazine dedicated to the 3D/2D assembly, packaging and test of semiconductor, MEMS and optoelectronic devices at the wafer level (WLP) and in single or 2D/3D multichip packages. Complete WDPI issues are available for download by packaging experts worldwide at our website.

Going forward, WDPI is the authoritative source for 3D/2D wafer level packaging, through silicon via interconnects, and the many 3D/2D IC/MEMS/optoelectronic device assembly and packaging technologies and processes including printed/embedded active and passive components in or on organic and inorganic substrates and interposers.

IC assembly, packaging, test, and advanced packaging— or back-end processing—are synonyms for component packaging, that vital link in microelectronics-centric high-tech manufacturing industries. Component packaging provides the crucial high-density interconnects for bare chips or devices enabling them to operate with other components in a functional package.

All components, including discrete ICs, MCPs (multichip packages), 2D multichip, 3D multichip stacked-die packages, MEMS/MOEMS, RF/wireless, photonic or other wafer-level fabricated devices, must be protected and interconnected. Each year, there are more mixes of device technologies within the final package. Package integration processing is the key to the successful development and manufacture of smaller, smarter, faster and increasingly mobile electronics products.

Ours is an electronics-centric world, where wafer, device and board/substrate/interposer interconnects/packaging efforts must be coordinated from conceptual design phases through numerous fabrication, assembly, packaging and interconnect schemes. Wafer-level packaging (WLP) has become an increasingly important solution since it is batch manufacturing—offering a compelling economic advantage that cannot be ignored.

Today, considerable efforts are devoted to hybrid WLCSP, wafer level chip scale packages, which use fab-like wafer processing technologies at the wafer level (photolithography processing. polymer coatings, sputtering, plating, thin-film etching and wafer probing) to produce wafers that are diced for the final complete CSPs.

Although semiconductor devices are crucial in electronic products, the device package itself can virtually become the product, as SEMI even acknowledged recently. With much discrete and IC production becoming a commodity, wafer fab ceased to be the highest value added segment of the manufacturing process. The value added distinction clearly shifted to test, assembly and packaging processes.

Many “system in package” configurations essentially become the end products. IC packaging and test, once considered a nuisance, is now the gating factor and can become the key product differentiator. IC chips need clever, pragmatic and reliable interconnect schemes to interface with substrates, interposers and products. These same devices need adequate protection from harsh operating environments and abuse encountered in assembly and in final products.

ICs, MEMS and optoelectronic device packages, in all their numerous manifestations, produced by both economical wafer-level batch processes as well as the many multichip 2D/3D variant packages, are the gatekeepers for much of the final cost and performance of electronic systems.