FEATURED ARTICLES

Wafer & Device Packaging and Interconnect, the preferred in-depth magazine for 3D WLP, TSV interconnects and 3D/2D multichip IC/MEMS/optoelectronic device assembly, packaging and test will have the following featured articles and columns in the September-October 2009 issue:

3D Packaging Interconnects for Mobile Internet Devices By Marc Robinson, Vertical Circuits Inc. A new low cost back-end 3D solution can be a very competitive alternative to TSVs for mobile Internet products. In 3D applications, interest is exponentially increasing in low cost, easy to implement packaging solutions that integrate increasing amounts of memory and other semiconductor devices in a wide variety of consumer products. A clear convergence of features and functionality is driving requirements for more silicon in smaller form factors. Portability and the desire for instant information access are the key factors in the adoption of new, innovative packaging solutions. Today’s users are unwilling to wait for their PCs and Macs to boot up to access email or the web. Instead, new handheld devices loaded with enhanced Capabilities now provide instant Internet access, 24/7. Engineers and designers are trying to squeeze smart phones, digital cameras, music players, GPS systems and other electronic devices with significant amounts of memory into a single, small package with unlimited battery life. New product categories, such as netbooks and solid state drives (SSDs), will benefit greatly from 3D packaging solutions, contributing significantly to the mobile Internet experience. While much interest and activity are directed toward through silicon via (TSV) solutions, many obstacles exist to widespread TSV adoption. As memory devices move from one lithography node to the next, the die get bigger at each successive generation, even though the area per bit shrinks, because of the memory progression to larger capacities per die. This increases end-product costs, as many TSV costs are wafer based, and hence the cost per die will increase as increases in die size reduce the number of die per wafer.

Wafer Bonding for 3D -Interconnect Applications By Thomas Glinsner, Peter Hangweier, Thomas Wagenleitner, Viorel Dragoi, EV Group Wafer bonding has been used for Micro-Electro-Mechanical Systems (MEMS) devices manufacturing for the last two decades. Combined with advanced packaging techniques such as wafer bumping, 3D interconnect, and chip scale packaging wafer bonding, it allows different components of an integrated circuit to be stacked (vertical integration concept) and directly connected, rather than side by side with printed circuit board (PCB) technology. The use of new packaging methods enables production of wafer-stacked IC´s with reduced cost, lower power consumption, small form factor, higher performance and increased yield and reliability. The 3D integration approach for silicon device manufacturing has great potential both from a technology, as well as from economic perspectives. The realization of vertical interconnected chips using Through-Silicon Vias (TSVs) is one of the key emerging trends in wafer level packaging. 3D integration can be seen as a paradigm shift of the semiconductor industry, which has improved device performances by shrinking gate dimensions according to Moore’s Law. Features size shrinking is getting more complex and costly as the semiconductor industry is moving towards double patterning with existing immersion lithography steppers and new patterning technologies like EUV-lithography. 3D integration, by exploiting the vertical dimension, provides an opportunity to continue to achieve the performance levels required by the extrapolation of Moore's law, but using a different technological approach (“More than Moore approach”). The rapid adoption of 3D integration technology seems to be essential as the industry paradigm is shifting to a new technology era that will offer tremendous global opportunities for expanded use of 3D silicon-based technologies in highly integrated systems. Aligned wafer bonding is one of the key technologies for 3D -IC devices manufacturing. Wafer bonding provides simultaneously mechanical and electrical interconnections between substrates, specifically important for 3D-IC applications. The main bonding techniques used now for 3D-IC are thermo-compression bonding (Cu-Cu bonding), adhesive bonding (e.g., BCB bonding) and silicon direct bonding. This article focuses on thermo-compression and Si direct bonding.

Pressure Indicating Film Characterization of Pressure Distribution in Eutectic Au/Sn Wafer-to-Wafer Bonding By D. Spicer, K. Lai, K. Kornelsen, A. Brennan, Micralyne Inc., N. Belov, M. Wang, Nanochip Inc.,T-K. Chou, J. Heck, Intel Corporation, T. Zhu, Nanochip Inc., S. Akhlaghi, Micralyne Inc. Pressure non-uniformity in a wafer-to-wafer bond chamber was characterized using pressure sensitive paper. The effect of poor pressure uniformity is discussed, and the non-uniformity was corrected for use in a eutectic Au/Sn based wafer -to-wafer bond. Several types of under solder metallization were investigated, with Nb/Au seed metal providing the best overall result with good solder compression, liquid proof seal, and minimal solder spill-out. Also, solder compression versus pressure applied was studied to achieve an excellent gap control (2 to 3 µm) between the bonded substrates. Wafer to wafer bonding has become an enabling semiconductor technology in industries such as 3D packaging, MEMS, MOEMS, and SOI. In a typical wafer bonding process, two flat substrates are permanently joined (bonded) to one another by applying physical pressure, temperature, and/or electric field. Each of the above factors is set depending on the substrate materials being bonded, and the control of these parameters is crucial to a successful, high-quality, high-uniformity manufacturing process.

Optimization of Wafer Level Test Hardware Using Signal Integrity Simulation By Jason Mroczkowski and Ryan Satrom, Everett Charles Technologies The wafer test industry is very competitive, with short time to market and low cost being the major driving forces. Today there is the option to help ensure performance of wafer test hardware prior to manufacturing, thus minimizing time to market and cost of test by using signal integrity simulation. Simulation provides confidence that the electrical performance of the test environment matches the requirements of the Device­Under-Test before fabrication. Simulation can also minimize or eliminate extensive lab testing, to allow a quicker path from fabrication to production.Wafer test simulation is focused on critical net signal integrity analysis. It encompasses any portion or all pieces in the path from the tester to the DUT. By focusing on the high-speed nets, the simulation environment can be minimized by ignoring all non-critical, non-high-speed nets. This allows design recommendations to be provided with confidence, without impacting lead times. This article describes a full test interface path. Simulation techniques used to capture each structure within that path are discussed. Most importantly, the structures and interfaces that must be captured in simulation to ensure the results match actual measurements are presented.

Flexible Substrates Improve Optoelectronic Components Packaging By Dr. Els Parton, Dr. Erwin Bosman, Dr. Geert Van Steenberge, IMEC Flexible substrates integrating electronic circuits are reaching maturity. But where does opto-electronics stand in this era of flexible and pliable substrates? Belgian researchers have come up with a new technology enabling an ultra thin, highly flexible package for opto-electronic components. Optoelectronics best known application field is in long -distance communication over fiber-optic cables. Besides this, the technology can also be used for short-distance data transfer for on board, rack to rack, board to board and chip to chip interconnections. Hybrid electro-optical boards are used with optical interconnections for the high­speed/bandwidth data transfer and electrical interconnections for the remaining ones. Flexible substrates are a well-known trend in the electronics packaging industry. Flexible electronics has found its way into the market at an astonishing speed during the last 10 years. The flexible behavior of substrates enables the third dimension in electronic interconnections with stacking and folding options. The dynamic flexibility has proven its usefulness in hinge -like interconnections and the static flexibility enables easy and reliable board to board connections and applications for non-flat surfaces. A final obstacle for total flexibility is, however, the rigidness of the electrical components. Standard packages are never flexible and more and more flex industries are leaning over to the mounting of thinne r bare chips by using flip chip technologies. Chips can however be thinned down to thicknesses of about 20 gm, but they hereby lose their usefulness for flip chip because of the handling problem, since very thin chips are fragile.

Factors Influencing Semiconductor Package Migration By Tom Strothmann and Kevin Kan, STATS ChipPAC, Inc. Semiconductor package selection and subsequent migration between package technologies is a key decision that is faced by both customers and suppliers in the industry today. Chip suppliers must understand the benefits of new package technologies and the available supply chain to ensure design wins into new products. Contract packaging suppliers must accurately predict market demand for new technologies to ensure the required infrastructure is ready to support it. Incorrect assessment of market demand results in poor allocation of capital or the inability to seize market opportunities on the part of the suppliers. The adoption of new package technology is a balance of competing forces that include cost, manufacturing complexity, package size, package performance, infrastructure momentum, and multiple sources of supply. Because of this complexity, it is often difficult to predict the tipping point for transition from one package type to another.

Wafer → WLCSP → Multi-die CSP Fabrication and use of Wafer Level Chip Scale Packaging By Jim Rates, Chip Supply, Inc. A customer came to us with a requirement for a 64 Mb x 72 DDR1 DRAM module. Their maximum available space was 32 mm square. This requirement presented several design and assembly challenges. Given the required MCM organization and the available die formats, we discovered that nine (9) die would be required. The smallest of the available die at the time would not fit in the available space without stacking. Our first approach was to stack two die on each of the substrate corners and assembly one die in the middle of the substrate. The bottom die in the stack would be flip chip attached and the top die mounted onto the back side of the bottom die and wire bonded to the substrate. The middle die would be flip chip mounted. This presented test problems. If each die is not tested at speed and burned in, MCM initial yield will be lower than acceptable as will the MCM infant mortality. Fortunately after first article build buy before production started, another semiconductor manufacturer released a physically smaller die in the correct configuration that enabled flip chip assembly of all nine die into a 25 mm x 32 mm area without stacking. We then chose to format the die as WLCSP to allow individual die test and burn-in prior to MCM assembly. The article explains how.

WDPI Columns: The Business of Doing Business: Business to Business in the HB-LED Industry By Dr. Robert N. Castellano, The Information Network The rapid proliferation of LEDs in various applications, including notebook PC screens, and automobile headlights, has spurred heavy capital investments by LED makers. We believe that strong worldwide LED adoption will drive significant growth in the LED business over the next several years. Currently 50% of the manufacturing cost of an LED is in the packaging. LED manufacturing cost reductions will come from a combination of improved LED efficiencies and drive current, larger wafers, more productive tools (higher throughput & yields – lower CoO), and better utilized tools (uptime).

2000 Plus 60 – The Future: Design 2060—Green, Clean and Lean Manufacturing By Dr. Ken Gilleo, ET-Trends The year is 2000 plus 60, a good time for green, clean and lean manufacturing. You’re a manufacturing systems designer in a world where few people work inside a production facility. Today, robots handle most of the in-factory tasks, even maintenance. Your “office”, or workspace, is in a wea ther-benign region of the Pacific. The one-kilometer diameter self-sustaining manmade island is a coveted location for younger technologists. While the zone is protected from storms by weather diversion technology, the stationary island can be propelled if required, but that means unhooking the plastic fiberoptic link. Work period is arriving so you activate lighting in your WEE room, the largest area of your abode — Workspace, Entertainment, and Education facility. You use a simple hand movement on the wall with an upward motion instead of the voice command alternative. You make a slight adjustment to the 6 luminescent walls with a few more touch movements. The wall color doesn’t suit your pensive, but creative mood, so you adjust the hue with another gesture. You could have your robot/mate select the lighting, but she always wants to add artificial windows that can be a distraction. A purist might gesture to bring up a control display on the wall with histograms, but the artist in you prefers to adjust by eye. Entertainment mode, with sophisticated dynamic lighting, graphics, sound, tactile and mind mod, is absolutely illegal during work period. But wait, there’s more...

From The Publisher By Dick Cowan Timely commentary on the business of wafer level packaging, TSVs and multichip assembly, packaging and test plus a zinger or two for those in related businesses.

From the Editor By Terrence Thompson The 2010s decade has arrived with a mind boggling array of assemably and packaging innovations! Some observations and analysis that cover the complex, interrelated wafer and device assembly, packaging and testing operations from a fresh manufacturing-slanted perspective will be covered. Where are the expert practitioners of 3D WLP, TSV interconnects and 3D/2D multichip IC/MEMS/optoelectronic device assembly, packaging and test headed? In this—and every—issue.